View SA9024_2666682.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

SA9024 900 mhz transmit modulator and 1.3 ghz fractionaln synthesizer objective specification 1997 aug 01 integrated circuits
philips semiconductors objective specification SA9024 900 mhz transmit modulator and 1.3 ghz fractionaln synthesizer 2 1997 aug 01 description this specification defines the requirements for a transmitter modulator and fractionaln synthesizer ic to be used in cellular telephones which employ the north american dual mode cellular system (is136). features ? low current from 3.75v supply ? low phase noise ? main loop with internal charge pump and fractional compensation ? 3line serial interface bus ? power down for the synthesizers ? speedup mode for faster switching applications ? cellular phones ? portable batterypowered radio equipment. general description the SA9024 bicmos device integrates: ? main channel synthesizer ? auxiliary synthesizer ? transmit offset synthesizer and oscillator ? i/q modulator ? power control ? reference and clock buffers ? control logic for programming and power down modes pin configuration sr01536 45 46 47 48 1 2 3 4 5 6 7 13 14 15 16 17 18 19 25 26 27 28 29 30 42 43 44 31 32 33 34 35 36 20 21 22 23 24 8 9 10 11 12 39 40 41 37 38 php v rx gnd gnd ipeak tank1 xtal tx data clock lock strobe gnd i q phi gnd rn gnd ina gnd pha rclk mclk tank2 vcc gnd gnd gnd gnd gnd dual gnd gnd cc v cc vcc v cc v cc v cc SA9024 lo1 rx lo2 tx lo1 tx lo2 phs out tx1 dual tx2 en 2 xtal 1 q i figure 1. pin configuration quick reference data symbol parameter conditions min. typ. max. unit v cc supply voltage v cc 3.6 3.75 3.9 v i cc supply current tbd ma i cc_save total supply current in powerdown mode tbd ma f vco input frequency 800 1300 mhz f aux input frequency 10 500 mhz f xtal crystal reference input frequency 10 40 mhz f pc maximum phase comparator frequency main and aux loops 5 mhz t amb operating ambient temperature 40 +85 c ordering information type number package name description version SA9024 lqfp48 plastic low profile quad flat package; 48 leads; body 7x7x1.4 mm sot313-2
philips semiconductors objective specification SA9024 900 mhz transmit modulator and 1.3 ghz fractionaln synthesizer 1997 aug 01 3 connections sr01455 php v rx gnd gnd ipeak tank1 xtal tx data clock lock strobe gnd i q phi gnd rn gnd ina gnd pha rclk mclk tank2 gnd gnd gnd gnd gnd dual gnd gnd cc v cc v cc v cc v cc lo1 rx lo2 tx lo1 tx lo2 phs out tx1 dual tx2 en xtal v cc v cc 2 main div. main pd and cp aux. div. aux pd and cp ref. div. control logic 0 90 0 90 0 90 ? 1 q i m n a figure 2. SA9024 block diagram
philips semiconductors objective specification SA9024 900 mhz transmit modulator and 1.3 ghz fractionaln synthesizer 1997 aug 01 4 pin descriptions pin no. pin description 1 php proportional charge pump output 2 v cc digital supply voltage 3 rx lo1 differential lo input 4 rx lo2 differential lo input 5 gnd digital ground 6 v cc tank supply voltage 7 tx lo1 differential transmit lo input 8 tx lo2 differential transmit lo input 9 gnd tank ground 10 phs out charge pump output (transmit offset) 11 i peak phs out current set resistor 12 tank1 vco differential tank 13 tank2 vco differential tank 14 v cc tx supply voltage 15 gnd tx ground 16 gnd tx ground 17 gnd tx ground 18 gnd tx ground 19 gnd tx ground 20 dualtx1 dual mode rf output 21 gnd tx ground 22 dualtx2 dual mode rf output 23 gnd tx ground 24 v cc tx supply voltage 25 q inverting quadrature input 26 q noninverting quadrature input 27 i noninverting in phase modulation input 28 i inverting in phase modulation input 29 v cc tx supply voltage 30 gnd tx ground 31 strobe data input latch enable 32 lock lock detect 33 clock serial clock input 34 data serial data input 35 tx en transmit enable 36 xtal 2 crystal oscillator emitter input 37 xtal 1 crystal oscillator base input 38 mclk buffered oscillator output 39 rclk buffered oscillator output 40 v cc ref supply voltage 41 pha auxiliary charge pump output 42 gnd ref ground 43 ina rx if input 44 v cc cp supply voltage 45 gnd cp ground 46 rn cp current set resistor 47 gnd cp ground 48 phi integral charge pump output
philips semiconductors objective specification SA9024 900 mhz transmit modulator and 1.3 ghz fractionaln synthesizer 1997 aug 01 5 operating modes & power down control there are two power saving modes of operation which the SA9024 can be put into, dependent on the status of the system. the intention of these different modes is to disable circuity that is not in use at the time in order to reduce power consumption. during sleep mode, only circuitry which is required to provide a master clock to the digital portion of the system is enabled. during receive mode, circuitry which is used to perform the receive function and provide a master clock is enabled. in transmit mode all the functions of the chip are enabled which are required to perform transmit, receive and provide master clock. SA9024 power mode truth table sleep mode receive mode transmit mode enabled yes no yes no yes no crystal oscillator 3 3 3 phase detector and charge pump (transmit offset) 3 3 3 vco 3 3 3 ssb up-converter 3 3 3 mclk buffer 3 3 3 rclk buffer 3 3 3 m offset loop divider 3 3 3 tx lo buffer 3 3 3 rx lo buffer 3 3 3 i/q modulator 3 3 3 variable gain amp. 3 3 3 control logic 3 3 3 main divider 3 3 3 reference divider 3 3 3 auxiliary divider 3 3 3 main phase detector and charge pump 3 3 3 auxiliary phase detector and charge pump 3 3 3 lock detect 3 3 3
philips semiconductors objective specification SA9024 900 mhz transmit modulator and 1.3 ghz fractionaln synthesizer 1997 aug 01 6 absolute maximum ratings symbol parameter value unit min. max. v cc supply voltage -0.3 +4.5 v v in voltage applied to any other pin -0.3 v cc +0.3 v p n power dissipation, t a = 25 c (still air) 980 mw t jmax operation junction temperature tbd c p max power input/output +10/+14 dbm i max dc current into any i/o pin -10 +10 ma t stg storage temperature 65 +150 c t o operating temperature -40 +85 c dc electrical characteristics v cc = +3.75 v; t a = 25 c; unless otherwise stated. symbo parameter test conditions limits units l parameter test conditions min typ max units v cc power supply range 3.6 3.75 3.9 v sleep mode 2 standby mode 17 i cc supply current operating: full power analog 95 ma cc y operating: full power digital dual 1 52 dual 1 52 i / i in-phase differential input quiescent v cc /2 v q / q quadrature phase differential input quiescent v cc /2 v v il clock, data, strobe, tx en input logic low 0.3 0.3 v cc v v ih clock, data, strobe, tx en input logic high 0.7 v cc v cc +0.3 v t a ambient temperature range -40 +25 +85 c digital outputs lock v o out p ut voltage low i o = 2ma 04 v v ol o u tp u t v oltage low i o = 2ma 0 . 4 v v oh output voltage high i o = -2ma v cc 0.4 v charge pump current setting resistor input; rn, r ipeak rn external resistor to ground 6 75 24 k rn e x ternal resistor to gro u nd 6 7 . 5 24 k r ipeak external resistor to ground 4.7 k v rn regulated voltage rn = 7.5 k 1.23 v v ipeak regulated voltage r ipeak = 4.7 k 1.3 v i peak phsout programming r ipeak = 4.7 k 0.26 ma phs gain phsout gain r ipeak = 4.7 k 24xi peak ma k pd phase gain transmit offset pll in phase lock 4.33 ma/rad charge pump outputs (including fractional compensation pump, not phs) rn = 7.5 k i o charge pump output current error 15 15 % i oph g versus expected current. 15 15 % i match sink to source current matching v phx = v cc /2 5 5 % current output variation versus v phx v phx in compliance range 10 10 % charge pump off, leakage current v phx = v cc /2 10 1 10 na v ph charge pump voltage compliance 3 0.7 v cc 0.8 v charge pump outputs (only phs) r ipeak = 4.7 k i o charge pump output current error 15 15 % i oph g versus expected current. 15 15 % i match sink to source current matching v phs = v cc /2 10 10 %
philips semiconductors objective specification SA9024 900 mhz transmit modulator and 1.3 ghz fractionaln synthesizer 1997 aug 01 7 current output variation versus v ph v phs in compliance range 25 25 % v ph charge pump voltage compliance 0.5 v cc 0.5 v ac electrical characteristics v cc = +3.75 v; t a = 25 c; unless otherwise stated. symbol parameter test conditions limits units symbol parameter test conditions min typ max units modulator tx o/ transmit lo input (ac-coupled; 50 w input power -13 -10 dbm tx lo 1/2 ( single-ended, 100 w differential) frequency range 900 1100 mhz vswr 2:1 tank1/2 vco tank differential inputs frequency range 90 180 mhz m pll offset divider maximum input frequency 180 mhz xtal 1 osc. transistor base osc. frequency 10 40 mhz xtal 2 osc. transistor emitter osc. frequency 10 40 mhz xo negative resistance 100 rclk, mclk reference buffer output frequency range output levels harmonic content z load = 5k w| | 7 pf 10 0.7 1.0 40 1.4 10 mhz v pp dbc tx en transmit enable transmit enable transmit disable tx en = 1 tx en = 0 logic q / q i / i baseband in-phase differential inputs maximum frequency diff. mod. level diff. input impedance dc bias point 1.8 0.8 10.0 1.8 0.9 v cc /2 1.0 2.55 mhz v p-p k w v tx rf tx rf operating range 820 920 mhz dual tx dual output se=1, tx en =1 (with external matching) (50 w ) amps/damps 820 853 mhz dual tx differential output, (dual tx ) open-collector, matched to 200 w differential impedance output level (avg. min., i and q quad., 0db vga) gain flatness +6.0 +10 1 +13.5 dbm db dual tx linearity worst case intermod. products (0db vga or +6 dbm, whichever is less, i & q in-phase) 3rd-order 5th-order 7th-order -42 -55 -65 -30 -45 -53 dbc dual tx carrier suppression (i & q in quadrature) vga = 0db vga = -38db -45 -33 -30 dbc dual tx sideband suppression (i & q in quadrature) -45 -32 dbc 2 to 284 mhz -45 824 to 849 mhz -47 dbc dual tx spurious output 849 to 869 mhz -45 869 to 894 mhz -104 dbm 894 to 8490 mhz -45 dbc tx lo -21 dual tx tx lo u p -conversion p roducts upper side band 21 dbc dual tx tx lo u - conversion roducts tx lo 3 tx offset -36 dbc harmonics 10th -21 dual tx broad-band noise (0db vga or +6 dbm, whichever is less) 869 to 894 mhz -123 dbm/hz dual adjacent channel noise p ower @30khz 95 dbc/hz dual tx adjacent channel noise po w er @ 30 kh z - 95 dbc/h z dual tx alternate channel noise power @ 60 khz 101 dbc/hz
philips semiconductors objective specification SA9024 900 mhz transmit modulator and 1.3 ghz fractionaln synthesizer 1997 aug 01 8 synthesizer main divider f mmax input frequency range 800 1300 mhz input harmonics no multiclocking 10 dbc rx lo 1/2 synthesizer lo input (ac-coupled; external shunt 50 w single-ended, 100 w differential) input power 20 0 dbm reference divider f rmax input frequency range 10 40 mhz input harmonics no multiclocking 10 dbc auxiliary divider f amax input frequency range 10 500 mhz input harmonics no multiclocking 10 dbc v ina input signal amplitude 0.200 v p-p serial interface f clock clock frequency 10 mhz t su set-up time: data to clock, clock to strobe 30 ns t h hold time: clock to data 30 ns clock 30 t sw pulse width strobe (b - d words) 30 ns t sw pulse width a word f 1 ref nref t w ns 1. transmit mode @ 33% duty cycle. 2. the relative output current variation is defined thus: i out /i out 2x i 2 i 1 ) |(i 2 +i 1 )|; with v 1 =0.7v, v 2 =v cc 0.8v (see figure 3) 3. power supply current measured with ? rx = 2100.54 mhz, ? ref = 19.44 mhz, ? ina = 109.92 mhz, main phase detector bias resistor = 7.5 k . main phase detector reference frequency = 240 khz, auxiliary phase detector frequency = 240 khz. 4. maximum and minimum levels guaranteed by design and random testing for temperature range of 40 to +85 c. 5. power is rated at i/q input level of 0.9v pp.
philips semiconductors objective specification SA9024 900 mhz transmit modulator and 1.3 ghz fractionaln synthesizer 1997 aug 01 9 i 2 i 1 i 2 i 1 v 1 v 2 current voltage sr00602 figure 3. output current definition
philips semiconductors objective specification SA9024 900 mhz transmit modulator and 1.3 ghz fractionaln synthesizer 1997 aug 01 10 functional description main channel synthesizer & auxiliary synthesizer serial input + program latches main dividers normal output charge pump integral output charge pump auxiliary output charge pump main phase detector main reference select speed-up output charge pump reference divider 2 2 2 auxiliary reference select auxiliary phase detector auxiliary divider data clock strobe inm1 inm2 inr ina fb rn php phi rn pha lock pd1 nmain fmod nf 16 3 fdac 8 2 pd1 nr pd1 + pd2 12 sa pd2 naux 2 sm pd2 2 2 14 fractional accumulator fb 1 sr01112 fdac 8 fdac 8 fdac 8 figure 4. synthesizer block diagram serial programming input the serial input is a 3-wire input (clock, data, strobe) used to program all counter ratios, dacs, selection and enable bits. the programming data is structured into 24-bit words; each word includes 2 or 3 address bits. figure [5] shows the timing diagram of the serial input. when strobe = l, the clock driver is enabled and on positive edges of the clock, the signal on data input is clocked into a shift register. when strobe = h, the clock is disabled and the data in the shift register remains stable. depending on the 2 or 3 address bits, data is latched into different working or temporary registers. in order to fully program the synthesizer, 3 words must be sent: a, b and c. the d word programs all other functions within the SA9024. those functions are
philips semiconductors objective specification SA9024 900 mhz transmit modulator and 1.3 ghz fractionaln synthesizer 1997 aug 01 11 power control, m (offset loop), se (tx offset loop synthesizer enable), dual mode, sleep mode 1 and sleep mode 2. the data for fdac is stored by the b word into a temporary register. when the a word is loaded, the data in this temporary register is loaded together with the a word into the work registers to avoid false temporary main synthesizer output caused by changes in fractional compensation. the a word contains new data for the main divider. the a word is loaded into the working registers only when a main divider synchronization signal is active to avoid phase jumps when reprogramming the main divider. the synchronization pulse is generated by the main divider when it has reached its terminal count, at which time a main divider output pulse is also sent to the main phase detector. this disables the loading of the a word each main divider cycle during maximum of (nref / ? ref ) seconds. therefore, to be sure that the a word will be correctly loaded, the strobe signal must be high for at least (nref / ? ref ) seconds. when programming the a word, the main charge pumps on output php and phi are set into the speedup mode as soon as the a word is latched into the working registers and remain so as long as strobe is held high. sr01447 data d0 clock strobe clock enabledshift in data clock disabled store data t su last clock first clock t su t h t su d1 d21 d23 d0 valid data change figure 5. serial input timing sequence
philips semiconductors objective specification SA9024 900 mhz transmit modulator and 1.3 ghz fractionaln synthesizer 1997 aug 01 12 table 1. function table symbol bits function fmod 1 fractional-n modulus selection flag: `0' = modulo 8 `1' = modulo 5 nf 3 fractional-n increment nmain 16 main divider ratio; 512 to 65,535 allowed nref 10 reference divider ratio; 4 to 1,023 allowed, rsm, rsa = a0 0o rsm 2 reference select for main phase detector rsa 2 reference select for auxiliary phase detector fdac 8 fractional compensation charge pump current dac naux 14 auxiliary divider ratio; 128 to 16,384 allowed cp 2 charge pump current ratio select (see table 1) ld 2 lock detect output select (see table 2) pd1 1 pd1 = 0 for power down; shuts off power to main divider and main chargepumps, anded with pd2 to turn off ref. divider. pd2 1 pd2 = 0 for power down; shuts off power to auxiliary divider, and auxiliary charge pumps; anded with pd1 to turn off ref. divider. pc 8 power control (see note 3) m 2 m, m = 6, 7, 8, 9 (see note 4) se 1 transmit offset synthesizer on/off tm 1 transmit mode: `0' = dual ad 1 mode control, 1 = digital; 0 = analog sm1 1 sleep mode 1 sm2 1 sleep mode 2 1. data bits are shifted in on the the leading clock edge, with the least significant bit (lsb) first and the most significant bit (msb) last. 2. on the rising edge of the strobe and with the address decoder output = 1, the contents of the input shift register are transferred to the working registers. the strobe rising edge comes one half clock period after the clock edge on which the msb of a word is shifted in. 3. the pc bits are used for the power control function. eight (8) bits of data allows for appropriate resolution of the power control. 00000000 = 0 db: 1 1111111 = 45.9 db (= 255 0.18). 4. the m bits are used to program the m counter for integer values between 6 and 9. 00 = 6, 01 = 7, 10 = 8, 11 = 9. 5. the tm bit is used to put the SA9024 into dual mode operation. in dual mode (tm = 0). 6. the ad bit allows a reduction in the linearity of the dual output driver while in amps mode. 7. the sm1 bit is used to shut down the tx lo buffers. sm1 = 1, buffers on; sm1 = 0, buffers off. 8. the sm2 bit is used to shut down the rclk buffer. sm2 = 1, buffer on; sm2 = 0, buffer off. 9. the se bit turns on and off the offset loop synthesizer circuits. se = 1, synthesizer on; se = 0, synthesizer off. 10. the lock bits determine what signal is present on the lock pin as follows: table 2. lock detect output select* lock lock pin function 00 main, auxiliary and offset lock condition 01 main and auxiliary lock condition 10 main lock detect condition 11 auxiliary lock condition *when a section is in power down mode, the lock indicator for that section is high.
philips semiconductors objective specification SA9024 900 mhz transmit modulator and 1.3 ghz fractionaln synthesizer 1997 aug 01 13 sr01449 d q clk (1) dq clk r q d v cc tx en temporary register se syn en (2) clock data working register r q strobe q q r clk (2) figure 6. transmit offset synthesizer reset circuit in figure 6, the falling edge of the strobe and address, inverted, toggles the q output of flip-flop (1) to a `1' state, enabling the phase detector, vco, divide by m, tx if buffer and ssb up-converter. approximately 80 m s after the synthesizer is locked, the tx en signal (enabled = 1) turns on the modulator and variable gain amplifier. the rising edge of tx en has no effect on syn en , however, the falling (rising inverted) edge toggles the q output of d flip-flop (2) to a `0' state. this disables the synthesizer, modulator and variable gain amplifier. to insure that slow edges on tx en do not cause improper operation, the tx en is a schmitt trigger design. the address decoder for program word `d' anded together with the strobe is used to load the contents of the temporary register into the working registers. d flip-flop (3) is used to prevent multiple strobe and address pulses in the event the address decoder output toggles on garbage bits during the time the strobe remains in a `1' state. the temporary register is common to the transmit offset synthesizer, main channel synthesizer and auxiliary synthesizer.
philips semiconductors objective specification SA9024 900 mhz transmit modulator and 1.3 ghz fractionaln synthesizer 1997 aug 01 14 txen strobe synen 80 s 6.67ms sr01538 figure 7. transmit offset synthesizer timing diagram
philips semiconductors objective specification SA9024 900 mhz transmit modulator and 1.3 ghz fractionaln synthesizer 1997 aug 01 15 data format format of programmed data last in msb serial programming format first in lsb p23 p22 p21 p20 ../.. ../.. p1 p0 a word, length 24 bits last in msb lsb first in address fmod fractionaln main divider ratio nmain spare 0 0 fmod nf2 nf1 nf0 n15 n14 n13 n12 n11 n10 n9 n8 n7 n6 n5 n4 n3 n2 n1 n0 sk1 sk2 default: 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 1 0 0 0 0 0 0 a word select fixed to 00. fractional modulus select fm 0=modulo 8, 1=modulo 5. fractionaln increment nf2..0 fractional n increment values 000 to 111. ndivider n0..n15, main divider values 512 to 65535 allowed for divider ratio. b word, length 24 bits address reference divider nref rsm rsa fractional compensation dac 0 1 r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 rsm 1 rsm 0 rsa 1 rsa 0 fdac 7 fdac 6 fdac 5 fdac 4 fdac 3 fdac 2 fdac 1 fdac 0 default: 0 0 0 1 0 1 0 0 0 1 0 0 0 0 x x x x x x x x b word select fixed to 01 rdivider r0..r9, reference divider values 4 to 1023 allowed for divider ration. charge pump current ratio cp1, cp0: charge pump current ratio, see table of charge pump currents. main comparison select rsm comparison divider select for main phase detector. aux comparison select rsa comparison divider select for auxiliary phase detector. fractional compensation fdac7..0, fractional compensation charge pump current dac, values 0 to 255. fdac = 77 for best op mod8. c word, length 24 bits address auxiliary divider naux cp lock pd spare 1 0 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 cp1 cp0 ld1 ld0 pd1 pd2 pd3 lod default 0 0 0 0 0 1 1 1 0 0 1 0 1 0 1 1 0 0 tx en tx en 0 0 c word select fixed to 10 adivider a0..a13, auxiliary divider values 128 to 16384 allowed for divider ratio. charge pump current ratio cp1, cp0: charge pump current ratio, see table fo charge pump currents. lock detect output ld1 ld0 0 0 combined main, aux. & offset loop lock detect signal present at the lock pin. 0 1 combined main and aux. lock detect signal present at the lock pin. 1 0 main lock detect signal present at the lock pin. 1 1 auxiliary loop lock detect signal present at the lock pin. when a section is in power down mode, the lock indicator for that section is high. power down pd1=1: power to ndivider, reference divider, main charge pumps, pd1=0 to power down. pd2=1: power to aux divider, reference divider, aux charge pump, pd2=0 to power down.
philips semiconductors objective specification SA9024 900 mhz transmit modulator and 1.3 ghz fractionaln synthesizer 1997 aug 01 16 table 3. main and auxiliary chargepump currents cp1 cp0 i pha i php i phpsu i phi_su 0 0 1.5xlset 3xiset 15xlset 36xlset 0 1 0.5xlset 1xlset 5xlset 12xlset 1 0 1.5xlset 3xlset 15xlset 0 1 1 0.5xlset 1xlset 5xlset 0 notes 1. i set = vset/rn; bias current for charge pumps. 2. cp1 is used to disable the phi pump. 3. iphp_su is the total current out of php in speedup mode. d word, length 24 bits address power control m divider se tm ad sleep mode test pa_current 1 1 0 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 m1 m0 se tm ad sm1 sm2 pai5 pai4 pai3 pai2 pai1 pai0 default: x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 d0 word select fixed to 110. output power control pc7(msb)...pc0(isb) provides output power attenuation for dual mode amplifier outputs in 0.18 db steps, fx = 45.9 db. m divider 00 = 6, 01 = 7, 10 = 8, 11 = 9 offset loop power down se offset loop synthesizer power down, se = 1 power on, se = 0 power down (sleep mode). dual mode select tm = 0 dualmode amps/damps mode select ad = 1 damps mode. ad = 0 amps mode tx buffers power down sm1 tx local oscillator buffers power down. sm1 = 1 power on, sm1 = 0 to power down. sm2 rclk buffer power down. sm2 = 1 power on, sm2 = 0 to power down. test: pa_current:pai tx test bits for controlling the current in the power amp. should be 0 during normal operation.
philips semiconductors objective specification SA9024 900 mhz transmit modulator and 1.3 ghz fractionaln synthesizer 1997 aug 01 17 modes of operation there are two power saving modes of operation which the circuit can be put into, dependent on the status of the system. the intention of these different modes is to disable circuitry that is not in use at the time in order to reduce power consumption. during sleep mode, only circuitry which is required to provide a master clock to the digital portion of the system is enabled. during receive mode, circuitry which is used to perform the receive function and provide a master clock is enabled. in transmit mode all the functions of the circuit are enabled which are required to perform transmit, receive and provide master clock. when the circuit is powered for the first time, it is in dual mode sleep. mode programming mode dual mode amps mode setting and blockstatus (x = on) sleep rx tx logic tx en 0 0 1 pd1 0 1 1 pd2 0 1 1 se>synen 0 0 1 tm 0 0 0 sm1 0 0 1 sm2 0 1 1 main loop, ndivider, rxlo buffer x x pd1 aux loop, adivider x x pd2 rdivider x x pd1 .or. pd2 offset vco, mdivider x se (+delay) see se>syn en diagram rcl buffer x x sm2 mcl buffer, reference input x x x 1 (always on) dual tx pa x (.not. tm) .and. tx en .and. sm1 txlo buffer, ssb upconverter x sm1 i/q modulator, vga x txen .and. sm1 control logic x x x 1 (always on) main divider the input signal on rx lo is amplified to a logic level by a balanced input comparator giving a common mode rejection. this input stage is enabled by serial control bit pd1 = 1. disabling means that all currents in the comparator are switched off. the main divider is built up to be a 16-bit counter. the loading of the work registers fmod, nf and nmain is synchronized with the state of the main counter to avoid extra phase disturbance when switching over to another main divider ratio as is explained in the serial programming input chapter. at the completion of a main divider cycle, a main divider output pulse is generated which will drive the main phase comparator. also, the fractional accumulator is incremented with nf. the accumulator works modulo q. q is preset by the serial control bit fmod to 8 when fmod = `0'. each time the accumulator overflows, the total divide ratio will be nmain + 1 for the next cycle. the mean division ratio over q main divider cycles will then be: nq nmain nf q synchronization is provided to avoid a random phase on the phase detector upon the loading of a new ratio and when powering up the loop. auxiliary divider the input signal on ina is amplified to logic level by a single-ended input buffer, which accepts low level ac-coupled input signals. this input stage is enabled if the serial control bit pd2 = `1'. disabling means that all currents in the buffer and prescaler are switched off. the auxiliary divider is programmed with 14 bits and has continuous integer division ratios over the range of 128 to 16,384. reference divider (figure 8) the input can be driven by a differential crystal input or an external tcxo. this input stage is enabled by the or function of the serial input bits pd1 and pd2. disabling means that all currents are switched off. the reference divider consists of a programmable divide by n ref (n ref = 4 to 1,023) followed by a 3-bit binary counter. the 2 bit sm determines which of the four output pulses is selected as the main phase detector signal. to obtain the best time spacing for the main and auxiliary reference signals, a different output will be used for the auxiliary phase detector, reducing the possibility of unwanted interactions.
philips semiconductors objective specification SA9024 900 mhz transmit modulator and 1.3 ghz fractionaln synthesizer 1997 aug 01 18 sr01440 rsa = a11o rsa = a10o rsa = a01o rsa = a00o rsm = a11o rsm = a10o rsm = a01o rsm = a00o main select auxiliary select reference input divide by nref /2 /2 /2 figure 8. reference variable divider phase detectors (figure 9) the auxiliary and main phase detectors each consist of a 2 d-type flip-flop phase and frequency detector. each flip-flop is set by the negative edge of the divider terminal count output pulse. the reset inputs are activated after a delay when both flip-flops have been set. this avoids non-linearity or dead-band around zero phase error. the flip-flops drive on-chip charge pumps. a pull-up current from the charge pump indicates the vco frequency shall be increased while a pull-down pulse indicates the vco frequency shall be decreased. current settings the ic has two current setting pins, rn and i peak . the active charge pump currents and the fractional compensation currents are linearly dependent on the current in the current setting pins. this current, i set , is set by an external resistor connected between the current setting pin and v ss . auxiliary output charge pumps the auxiliary charge pumps on pin pha are driven by the auxiliary phase detector and the current value is determined by the external resistor attached to pin rn.
philips semiconductors objective specification SA9024 900 mhz transmit modulator and 1.3 ghz fractionaln synthesizer 1997 aug 01 19 sr01451 r x p n ref divider aux/main divider d q clk a1o r d r clk a1o x q n p t v dda gnd ph v ssa ptype charge pump ntype charge pump r inr inr i ph figure 9. phase detector structure with timing main output charge pumps and fractional compensation currents the main charge pumps on pin php and phi are driven by the main phase detector. the current value is determined by the current at pin rn. the fractional compensation current is linearly dependent on the main charge pump current and its level relative to the main charge pumps is set by an 8-bit programmable dac. the timing for the fractional compensation is derived from the main divider. the current level based on the value of frd, fdac and i set . figure 10 shows the waveforms (not to scale) for a typical base.
philips semiconductors objective specification SA9024 900 mhz transmit modulator and 1.3 ghz fractionaln synthesizer 1997 aug 01 20 sr01454 reference r main m vco cycles n n n+1 n n+1 detector output accumulator 241 3 0 fractional compensation current output on php, phi pulse width modulation pulse level modulation ma m a contents figure 10. waveforms for nf = 2; fraction = 0.4 figure 10 shows that for a proper fractional compensation, the area of the fractional compensation current pulse must be equal to the area of the charge pump ripple output. the fractional compensation current is derived from the main charge pump in that it will follow all the current scaling through external resistor setting, programming or speedup operation. for a given pump, |comp |pump 128 x fdac 5 x 128 xfrd where: icomp is the compensation current, ipump is the pump current, fdac is the fractional dac value and frd is the fractional accumulator value. the theoretical value for fdac would then be: 128 for fmod = 1 (modulo 5) and 80 for fmod = 0 (modulo 8). when the serial input a word is loaded, the output circuits are in the aspeedup modeo as long as the strobe is h, otherwise the anormal modeo is active. lock detect the output lock maintains a logic `1' when the auxiliary phase detector anded with the main phase detector anded with offset phase detector indicates a lock condition. during the standby mode of operation when the offset loop is unlocked, (syn en = low see figure 6), the offset phase detector lock output is forced to an on (locked) state so that the lock detect will give an indication of receiver lock. the lock condition for the main and auxiliary synthesizers is defined as a phase difference of less than 1 cycle on the reference input inr. the lock condition is also fulfilled when the relative counter is disabled (pd1 = `0' or pd2 = `0') for the main or auxiliary counter, respectively. functional description of offset loop, modulator and power control transmit offset synthesizer the transmit offset phase locked loop portion of the SA9024 design consists of the following functional blocks: reference oscillator, limiters, phase detector, m, if vco and passive loop filter. harmonic contents of this signal are attenuated by an lp filter. the output of the if vco is also divided by n and compared with the reference oscillator in the phase detector. reference oscillator this oscillator is used to generate the reference frequency together with an external crystal and varicap. the output is internally routed to three buffers and a phase comparator. it is possible to run the oscillator as an amplifier from an external reference signal (tcxo). phase detector and charge pump the phase comparator is used to compare the output of the divider with the reference. it provides an output proportional to the phase difference between the divided down vco and the reference. this output is then filtered and used as the control voltage input to the vco. the phase detector is a gilbert multiplier cell type, having a linear output from 0 to p ( p /2 p /2), followed by a charge pump. the charge pump peak output current is programmable to 6.4ma via the use of an external resistor. a preliminary design analysis has been performed with the following loop parameters:
philips semiconductors objective specification SA9024 900 mhz transmit modulator and 1.3 ghz fractionaln synthesizer 1997 aug 01 21 a lock detect signal is provided and anded together with lock detect signals from both the main channel synthesizer and auxiliary synthesizer. while in standby mode, the lock detect signal will be forced to a valid lock state so that the lock detect signal will indicate when the main and auxiliary phase detectors have achieved phase lock. divide by m the m is a 2-bit programmable divider which can be configured for ney integer divide from 6 to 9. the divider is used to convert the vco output down to the reference frequency before feeding it into the phase comparator. vco this oscillator is used to generate the transmit if frequency between 90mhz and 180mhz. the vco tank is configured using a parallel inductor tuning varactor diode. dc blocking capacitors are used to isolate the varactor control voltage from the vco tank dc bias voltages. ssb up-converter and tx if buffer the tx if buffer provides isolation between the ssb up-converter and the vco output. the single sideband up-converter (ssb) is an active gilbert cell multiplier (matched pair), combined with two quadrature phase shift networks and a low pass filter. the ssb up-converter is used to reject the unwanted upper sideband that would normally occur during the up-conversion process. i/q modulator the quadrature modulator is an active gilbert cell multiplier (matched pair) with cross coupled outputs. these outputs are then provided to the variable gain amplifier. when the in-phase input i = cos ( w t) and the quadrature-phase input q = sin ( w t) (i.e., q lags i by 90 ), the resulting output should be upper single sideband. variable gain amplifiers the variable gain amplifiers are used to control the output level of the device, with a power control range of 45.9db. the output stages are differential, matched from 200 w to 50 w . power control the power control range should be greater than or equal to 45.9db, having a monotonically decreasing slope, with 0db = +11.5 dbm nominal. eight bits are available for power control programming. the top 6 bits (pc7 to pc2) provide coarse attenuation with .6db step size accuracy. the bottom 2 bits provide fine attenuation with .18 db step size accuracy. sr01453 maximum accumulated error (not to scale) top 12 db fine step acuracy bottom 25 db coarse step ac- curacy +11.5 3 15 26 28 0 12 24 38 45.9 vga setting (db) power out (dbm nom) figure 11. power control oscillator buffers there are three buffers for the reference signal, two of which are used to provide external reference signals. the internal reference signal is used for the main and auxiliary synthesizer reference. the second buffer (mclk) is used as a master clock for external digital circuitry which is always on, while the third buffer (rclk) is used as a clock for external digital circuitry which is not used in sleep mode. lo buffers the lo buffers are used to provide isolation for the vco and between the transmitter up-converter and channel synthesizer.
900 mhz transmit modulator and 1.3 ghz fractionaln synthesizer philips semiconductors objective specification SA9024 1997 aug 01 22 lqfp48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm sot313-2
900 mhz transmit modulator and 1.3 ghz fractionaln synthesizer philips semiconductors objective specification SA9024 1997 aug 01 23 philips semiconductors and philips electronics north america corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performanc e. philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under a ny patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copy right, or mask work right infringement, unless otherwise specified. applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. life support applications philips semiconductors and philips electronics north america corporation products are not designed for use in life support appl iances, devices, or systems where malfunction of a philips semiconductors and philips electronics north america corporation product can reasonab ly be expected to result in a personal injury. philips semiconductors and philips electronics north america corporation customers using or sel ling philips semiconductors and philips electronics north america corporation products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors and philips electronics north america corporation for any damages resulting from such improper use or sale. this data sheet contains preliminary data, and supplementary data will be published at a later date. philips semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. philips semiconductors 811 east arques avenue p.o. box 3409 sunnyvale, california 940883409 telephone 800-234-7381 definitions data sheet identification product status definition objective specification preliminary specification product specification formative or in design preproduction product full production this data sheet contains the design target or goal specifications for product development. specifications may change in any manner without notice. this data sheet contains final specifications. philips semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product. philips semiconductors and philips electronics north america corporation register eligible circuits under the semiconductor chip protection act. ? copyright philips electronics north america corporation 1997 all rights reserved. printed in u.s.a. print code date of release: 05-96 document order number:

▲Up To Search▲

Price & Availability of SA9024

	To Download SA9024 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .